The present application relates to a silicon germanium (SiGe) graded buffer layer. More particularly, the present application relates to a SiGe graded buffer layer containing a high germanium percentage (40 atomic percent Ge or greater) in which stacking fault formation and threading arm dislocation density are drastically reduced.
Graded buffer layers (GBLs), also referred to as strain relaxed buffer layers (SRBs), are currently one of the front up approaches for 7 nm node and beyond technologies, enabling, for instance, dual channel material FinFETs or nanosheets on the same substrate. As an example, a topmost silicon germanium alloy (i.e., SiGe) of a GBL can be used for growing tensily-strained silicon (Si) channels for n-channel field effect transistors (i.e., nFETs), and compressively-stained germanium or high germanium percentage SiGe channels for p-channel field effect transistors (i.e., pFETs).
One of the biggest challenges with the process device yields of conventional GBLs is that the defect density at the surface of the GBL is in the 1×105 range even for the best known structures. This level of defect density is far too high to achieve high performance complementary metal oxide semiconductor (CMOS) fabrication. As such, a method is needed in which GBLs can be formed in which the defect density at the surface of each SiGe layer of a GBL is reduced to allow the GBLs to be employed in high performance CMOS fabrication.
In prior SiGe graded buffer layers, a first low percentage SiGe layer, often a 500-600 nm layer of 4-5% SiGe, grows fully strained onto a silicon substrate (compressive strain). Also the next layer, typically a 8-10% SiGe layer with a thickness of 500-600 nm, grows fully strained onto the underlying 4-5% SiGe layer. Both are fully strained since each of the SiGe layers is still below the critical thickness for such low germanium concentrations, even with their combined thickness of 1-1.2 micron. Once the 12% SiGe layer is grown and the higher percentage SiGe layers, the graded buffer layer starts to relax. Relaxation is accommodated by misfit dislocations at the interface between the two lattice mismatched semiconductor materials. The misfit dislocations lie at the interface, but have two threading arms (i.e. threading arm dislocations) that extend all the way to the surface. Threading arm dislocations are defects which are detrimental to devices build onto those GBL substrates. From each SiGe layer, two threading arm dislocations penetrate to the surface.
One way to reduce the threading arm dislocations is to grow the last SiGe layer of the target percentage thick, say 2-3 micron thick. This will lead to the annihilation of some of the threading arm dislocations. Also growing each of the strain relaxing SiGe layers thicker will reduce surface defect densities. The best 5 micron thick SiGe layers have defect densities of 1-2×105/cm2. Increasing the thickness to 7-8 micron, defect densities of 4-7×104/cm2 can be accomplished. What is needed, however, is defect numbers below 100/cm2, with 1 to 0.1/cm2 preferred. The above description applies to 20% SiGe graded buffer layers.
An additional problem is the formation of stacking faults. In a SiGe alloy containing 20 atomic percent Ge, the stacking fault density is low and negligible. However, SiGe graded buffer layers having a topmost SiGe layer having 25 atomic percent Ge or greater will have high dislocation defect densities and the formation of stacking faults will increase.
A way to reduce stacking fault formation and dislocation defect density is needed to facilitate the application of high germanium percentage SiGe graded buffer layers.